PSD835G2V - STMicroelectronics

PSD835G2V Flash PSD

. . . 11 1.1 In-system programming (ISP) via JTAG . . . . . . . . 11 1.1.1 1.1.2 1.1.3 First time programming . 11 Inventory build-up of pre-programmed devices . .

Features

■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs Dual bank Flash memories
  – 4 Mbits of Primary Flash memory (8 uniform sectors, 64 Kbyte)
  – 256 Kbits of secondary Flash memory with 4 sectors
  – Concurrent operation: READ from one memory while erasing and writing the other 64 Kbit of battery-backed SRAM 52 reconfigurable I/O ports Enhanced JTAG serial port PLD with macrocells
  – Over 3000 gates of PLD: CPLD and DPLD
  – CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs)
  – DPLD - user defined internal chip select decoding 52 individually configurable I/O port pins Th.