PLS173 - NXP

PLS173 Programmable logic array 22 x 42 x 10

The PLS173 is a two-level logic element consisting of 42 AND gates and 10 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 12 inputs (I) and 10 bidirectional I/O lines (B). These yield variable I/O gate configurations via 10 direction control gates (D), ranging from 22 inputs to 10 outputs. On-chi.

Features

• I/O propagation delay: 30ns (max.)
• 12 inputs
• 42 AND gates
• 10 OR gates
• 10 bidirectional I/O lines
• Active-High or -Low outputs
• 42 product terms:
  – 32 logic terms
  – 10 control terms PIN CONFIGURATIONS N Package I0 1 I1 2 I2 3 I3 4 I4 5 I5 6 I6 7 I7 8 I8 9 I9 10 I10 11 GND 12 N = Plastic DIP (300mil-wide) 24 VCC 23 B9 22 B8 21 B7 20 B6 19 B5 18 B4 17 B3 16 B2 15 B1 14 B0 13 I11
• Ni-Cr programmable links
• Input loading:
  –100µA (max.)
• Power dissipation: 750mW (typ.)
• 3-State outputs
• TTL compatible APPLICATIONS A Package I3 4 I2 3 I1 2 I0 VCC B9 B8 1 28 27 26 25 NC 24 B7 23 B.