PI7C8150B - Pericom Semiconductor Corporation

PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

First Release of Data Sheet Correction to description for bit[0] at offset 48h. Changed from Memory Read Flow Through Disable to Memory Read Flow Through Enable. Added reset condition to offset 4Ch, bits [31:28] Revised descriptions and added ordering information for PI7C8150B-33 (33MHz) device 06/10/03 1.02 Revised temperature support to industrial temper.

Features

section in the introduction Revised register description bits[31:24] offset 18h - Secondary Latency Timer Register (section 14.1.13) Revised register description for bits[3:2] offset 48h
  – Extended Chip Control Register (section 14.1.31) Corrected configuration register offset 80h (bit[15:0] is secondary bus master timeout counter and bit[31:16] is primary bus master timeout counter) Revised and added further descriptions for bit[15:0] offset 80h and bit[31:16] offset 80h Corrected Note 4 to show REQ_L has a setup time of 12ns and GNT_L has a setup time of 10ns (section 17.3) Removed ‘Advance .