PI6C5930 - Pericom Semiconductor

PI6C5930 Low Skew CMOS PLL Clock Driver

The PI6C5930 clock driver uses a PLL (phase-locked loop) to reduce time skew between a reference clock input (SYNC) and the outputs. An internal loop filter eliminates the need for external compensation. This driver generates six clock outputs: Q0 through Q4 running at the same frequency, plus Q/2 which runs at one half the frequency of Q0-Q4. Thanks to desi.

Features

• Wide frequency range: 100 MHz max.
• Five Q and one Q/2 outputs
• Output skew < 250ps (rising edges)
• Internal RC loop filter network
• Low noise TTL-compatible outputs
• Balanced drive outputs: +24mA
• Outputs Hi-Z and registers reset when OE = LOW
• PLL bypass for testing and low-frequency applications
• Small footprint 20-pin QSOP package (Q) Description The PI6C5930 clock driver uses a PLL (phase-locked loop) to reduce time skew between a reference clock input (SYNC) and the outputs. An internal loop filter eliminates the need for external compensation. This driver generates six clock .