NT5DS32M8CT - Nanya Techology

NT5DS32M8CT 256Mb SDRAM

NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT, NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS, and NT5DS16M16CG are die C of 256Mb SDRAM devices based using DDR interface. They are all based on Nanya’s 110 nm design process. Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read.

Features

CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 (5T) (6K/6KL) 133 166 166 200 -
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• DDR 256M bit, die C, based on 110nm design rules
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL align.