MT48LC1M16A1 - Micron

MT48LC1M16A1 SYNCHRONOUS DRAM

The 16Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 16,777,216 bits. It is internally configured as a dual 512K x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16-bit banks is organized as 2,048 rows by 256 columns by 16 bits. Read and write accesse.

Features

• PC100 functionality
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge 1 Meg x 16 - 512K x 16 x 2 banks architecture with 11 row, 8 column addresses per bank
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge Mode, includes CONCURRENT AUTO PRECHARGE
• Self Refresh and Adaptable Auto Refresh Modes - 32ms, 2,048-cycle refresh or - 64ms, 2,048-cycle refresh or - 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outpu.