MIMX9352DVVXMAB - NXP

MIMX9352DVVXMAB i.MX 93 Application Processors

NXP Semiconductors Data Sheet: Technical Data Document Number: IMX93CEC Rev. 3, 12/2023 i.MX 93 Application Processors Data Sheet for Commercial Products MIMX9352DVVXMAB MIMX9332DVVXMAB MIMX9302DVVXDAB MIMX9322DVXXMAB MIMX9312DVXXMAB MIMX9351DVVXMAB MIMX9331DVVXMAB MIMX9301DVVXDAB MIMX9321DVXXMAB MIMX9311DVXXMAB Package Information Plastic Package FCBGA.

Features

(Sheet 1 of 3) Features Two Cortex®-A55 processors operating up to 1.7 GHz
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• 64 KB per-core L2 cache
• Media Processing Engine (MPE) with Arm® NeonTM technology supporting the Advanced Single Instruction Multiple Data architecture
• Floating Point Unit (FPU) with support of the Arm® VFPv4-D16 architecture Support of 64-bit Arm® v8.2-A architecture 256 KB cluster L3 cache Parity/ECC protection on L1 cache, L2 cache, and TLB RAMs
• Stand by monitoring with Cortex®-A55 and other high-power modules power gated Cortex®-M33 CPU operating up to 250 M.