MIMX9351CVUXMAA - NXP

MIMX9351CVUXMAA Application Processors

NXP Semiconductors Data Sheet: Technical Data Document Number: IMX93IEC Rev. 1, 04/2023 i.MX 93 Industrial Application Processors Data Sheet A0 Pre-Production Prototype MIMX9352CVUXMAA MIMX9332CVUXMAA MIMX9302CVUXDAA MIMX9322CVWXMAA MIMX9312CVWXMAA MIMX9351CVUXMAA MIMX9331CVUXMAA MIMX9301CVUXDAA MIMX9321CVWXMAA MIMX9311CVWXMAA Package Information Plasti.

Features

(Sheet 1 of 3) Features Two Cortex®-A55 processors operating up to 1.7 GHz
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• 64 KB per-core L2 cache
• Media Processing Engine (MPE) with Arm® NeonTM technology supporting the Advanced Single Instruction Multiple Data architecture
• Floating Point Unit (FPU) with support of the Arm® VFPv4-D16 architecture Support of 64-bit Arm® v8.2-A architecture 256 KB cluster L3 cache Parity/ECC protection on L1 cache, L2 cache, and TLB RAMs
• Stand by monitoring with Cortex®-A55 and other high-power modules power gated Cortex®-M33 CPU operating up to 250 M.