ESMT M13S64164A DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS .
z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe (DQS) z DQS is edge-aligned with data for reads; center-aligned with data for WRITE z Data mask (DM).
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | M13S64164A-6BG2Y |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
2 | M13S64164A-6TG |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
3 | M13S64164A-6TG2Y |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
4 | M13S64164A-4BG2Y |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
5 | M13S64164A-4TG2Y |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
6 | M13S64164A-5BG |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
7 | M13S64164A-5BG2Y |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
8 | M13S64164A-5TG |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
9 | M13S64164A-5TG2Y |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
10 | M13S128168A |
Elite Semiconductor Memory Technology |
2M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
11 | M13S128324A |
ESMT |
Double Data Rate SDRAM | |
12 | M13S2561616A |
Elite Semiconductor Memory Technology |
4M x 16 Bit x 4 Banks Double Data Rate SDRAM |