(M13S32321A) Pin Name Function Address inputs - Row address A0~A9 - Column address A0~A7 A8/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi- directional Data Strolle. Pin Name M13S32321A Function A0~A9, BA0,BA1 DQ0~3 DQ Mask enable in write cycle. DQ0~DQ31 RAS .
z z z z z z z z z z z z z z z z z z z M13S32321A 256K x 32 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 3; 4 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | M13S128168A |
Elite Semiconductor Memory Technology |
2M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
2 | M13S128324A |
ESMT |
Double Data Rate SDRAM | |
3 | M13S2561616A |
Elite Semiconductor Memory Technology |
4M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
4 | M13S256328A |
Elite Semiconductor Memory Technology |
2M x 32 Bit x 4 Banks Double Data Rate SDRAM | |
5 | M13S5121632A |
ESMT |
Double Data Rate SDRAM | |
6 | M13S64164A-4BG2Y |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
7 | M13S64164A-4TG2Y |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
8 | M13S64164A-5BG |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
9 | M13S64164A-5BG2Y |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
10 | M13S64164A-5TG |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
11 | M13S64164A-5TG2Y |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM | |
12 | M13S64164A-6BG |
ESMT |
1M x 16 Bit x 4 Banks Double Data Rate SDRAM |