K7P403622M - Samsung

K7P403622M SRAM

Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Asynchronous Power Down Core Power Supply Pin Name VDDQ M1, M2 .

Features

• 128Kx36 or 256Kx18 Organizations.
• 3.3V Core Power Supply.
• LVTTL Input and Output Levels.
• Differential, PECL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm) Organization Part Number 128Kx36 256Kx18 K7P403622M-H20 K7P403622M-H16 K7P403622M-H19 K7P4.