K7P321874C - Samsung Electronics

K7P321874C 1Mx36 & 2Mx18 SRAM

The K7P323674C and K7P321874C are 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of 36 bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology. Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising e.

Features

• 1Mx36 or 2Mx18 Organizations.
• 1.8 or 2.5V VDD/1.5V ~1.8VDDQ.
• HSTL Input and Output Levels.
• Differential, HSTL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write. Preliminary www.DataSheet4U.com 1Mx36 & 2Mx18 SRAM
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• Programmable Impedance Output Drivers.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm.