K7P323688M - Samsung Electronics

K7P323688M 1Mx36 & 2Mx18 SRAM

Pin Name K, K SAn DQn SS SW SWa SWb SWc SWd M 1 , M2 G Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Select Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Read Protocol Mode Pins (M1=VSS, M2=VDDQ.

Features

• 1Mx36 or 2Mx18 Organizations.
• 1.8V VDD/1.5V or 1.8V VDDQ.
• HSTL Input and Output Levels.
• Differential, HSTL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1).
• 119(7x17) Flip Chip Ball Grid Array Package(14mmx22mm). Org. 1Mx36 2Mx18 1Mx36 & 2Mx18 SRAM .