IW4042B - IK Semiconductor

IW4042B Quad Clocked D-Latch

TECHNICAL DATA IW4042B Quad Clocked «D» Latch High-Voltage Silicon-Gate CMOS IW4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical. Information present at the data i.

Features

D and F suffixes); 16-lead dual-in-line plastic package (E suffix), and in chip form (H suffix).
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4042BN Plastic IW4042BD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT FUNCTION TABLE Inputs Clock Polarity 0 0 1 1 Outputs Q D Latch D Latch w w w .d e e h s a t a . u t4 m o c 0 1 1 0 PI.