The 36 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state.
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP package
• Power supply:
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
• .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | IS61NVP102418 |
ISSI |
(IS61NVPxxxxx) STATE BUS SRAM | |
2 | IS61NVP102418B |
ISSI |
18Mb STATE BUS SYNCHRONOUS SRAM | |
3 | IS61NVP10018 |
ISSI |
(IS61NVP10018 / IS61NVP51236) State Bus SRAM | |
4 | IS61NVP12818A |
ISSI |
(IS61NVPxxxxxA) STATE BUS SRAM | |
5 | IS61NVP12836A |
ISSI |
(IS61NVPxxxxxA) STATE BUS SRAM | |
6 | IS61NVP204818A |
Integrated Silicon Solution |
36Mb STATE BUS SRAM | |
7 | IS61NVP204836B |
Integrated Silicon Solution |
PIPELINE (NO WAIT) STATE BUS SRAM | |
8 | IS61NVP25618A |
ISSI |
(IS61NVPxxxxxA) STATE BUS SRAM | |
9 | IS61NVP25636A |
ISSI |
9Mb STATE BUS SRAM | |
10 | IS61NVP25636B |
ISSI |
9Mb STATE BUS SRAM | |
11 | IS61NVP25672 |
ISSI |
(IS61NVPxxxxx) STATE BUS SRAM | |
12 | IS61NVP409618B |
Integrated Silicon Solution |
PIPELINE (NO WAIT) STATE BUS SRAM |