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The 18 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorp.
www.DataSheet4U.com ISSI JULY 2006 ® DESCRIPTION The 18 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | IS61NVP102418B |
ISSI |
18Mb STATE BUS SYNCHRONOUS SRAM |
|
| 2 | IS61NVP102436A |
Integrated Silicon Solution |
36Mb STATE BUS SRAM |
|
| 3 | IS61NVP10018 |
ISSI |
(IS61NVP10018 / IS61NVP51236) State Bus SRAM |
|
| 4 | IS61NVP12818A |
ISSI |
(IS61NVPxxxxxA) STATE BUS SRAM |
|
| 5 | IS61NVP12836A |
ISSI |
(IS61NVPxxxxxA) STATE BUS SRAM |
|
| 6 | IS61NVP204818A |
Integrated Silicon Solution |
36Mb STATE BUS SRAM |
|
| 7 | IS61NVP204836B |
Integrated Silicon Solution |
PIPELINE (NO WAIT) STATE BUS SRAM |
|
| 8 | IS61NVP25618A |
ISSI |
(IS61NVPxxxxxA) STATE BUS SRAM |
|
| 9 | IS61NVP25636A |
ISSI |
9Mb STATE BUS SRAM |
|
| 10 | IS61NVP25636B |
ISSI |
9Mb STATE BUS SRAM |
|
| 11 | IS61NVP25672 |
ISSI |
(IS61NVPxxxxx) STATE BUS SRAM |
|
| 12 | IS61NVP409618B |
Integrated Silicon Solution |
PIPELINE (NO WAIT) STATE BUS SRAM |
|