ISSI's 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. The 512Mb DDR2 SDRAM is provided in a wide bus x32 format, designed to offer a smaller footprint and.
• Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Double data rate interface: two data transfers per clock cycle
• Differential data strobe (DQS, DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, and 6 supported
• Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength, full and reduce.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | IS46DR32801A |
ISSI |
8Mx32 256Mb DDR2 DRAM | |
2 | IS46DR32801B |
ISSI |
256Mb DDR2 DRAM | |
3 | IS46DR16128C |
ISSI |
DDR2 DRAM | |
4 | IS46DR16160B |
ISSI |
DDR2 DRAM | |
5 | IS46DR16320B |
ISSI |
512Mb DDR2 SDRAM | |
6 | IS46DR16320D |
ISSI |
DDR2 DRAM | |
7 | IS46DR16320E |
ISSI |
DDR2 DRAM | |
8 | IS46DR16640B |
ISSI |
1Gb DDR2 SDRAM | |
9 | IS46DR16640BL |
ISSI |
1Gb DDR2 SDRAM | |
10 | IS46DR16640C |
ISSI |
DDR2 DRAM | |
11 | IS46DR16640D |
ISSI |
64Mx16 DDR2 DRAM | |
12 | IS46DR16640DL |
ISSI |
64Mx16 DDR2 DRAM |