IDT71V67702 - IDT

IDT71V67702 (IDT71V67702 / IDT71V67902) Burst Counter Flow-Through Outputs / Single Cycle Deselect

The IDT71V67702/7902 are high-speed SRAMs organized as 256K x 36/512K x 18. The IDT71V67702/7902 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write.

Features

x x x x x x x x 256K x 36, 512K x 18 memory configurations Supports fast access times:
  – 7.5ns up to 117MHz clock frequency
  – 8.0ns up to 100MHz clock frequency
  – 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 2.5V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA). Description The IDT71V677.