ICS93732 Low Cost DDR Phase Lock Loop Zero Delay Buffer Datasheet

ICS93732 Low Cost DDR Phase Lock Loop Zero Delay Buffer

Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz (DDR 533) • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • CYCLE - CYCLE jitter (66MHz): <120ps • CYCLE - CYCLE jitter (>100MHz): <65ps • C.

Features

• Low skew, low jitter PLL clock driver
• Max frequency supported = 266MHz (DDR 533)
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• 3.3V tolerant CLK_INT input Switching Characteristics:
• CYCLE - CYCLE jitter (66MHz): <120ps
• CYCLE - CYCLE jitter (>100MHz): <65ps
• CYCLE - CYCLE jitter (>200MHz): <75ps
• OUTPUT - OUTPUT skew: <100ps
• DUTY CYCLE: 49.5% - 50.5% Pin Configuration DDRC0 1 DDRT0 2 VDD 3 DDRT1 4 DDRC1 5 GND 6 SCLK 7 CLK_INT 8 N/C 9 VDDA 10 GND 11 VDD 12 DDRT2 13 DDRC2 14 ICS93732 28 GND 27 DDRC5.

The same part from a different manufacturer

ICS93732 - Renesas

Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz (DDR 533) • I2C for functional and .

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ICS93732 - Integrated Circuit Systems