ICS93705 DDR Phase Lock Loop Zero Delay Clock Buffer Datasheet

ICS93705 DDR Phase Lock Loop Zero Delay Clock Buffer

Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz): <120ps • PEAK - PEAK jitter (>100MHz): <75ps • CYCLE - CYCLE jitter (66MHz):<120ps • CYCLE - CYCL.

Features

• Low skew, low jitter PLL clock driver
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• 3.3V tolerant CLK_INT input Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (66MHz):<120ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 450ps - 950ps
• DUTY CYCLE: 49% - 51% GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT N/C VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND Pi.

The same part from a different manufacturer

ICS93705 - Renesas

Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to o.

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ICS93705 - Integrated Circuit Systems