The ICS2510C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICS2510C operates at 3.3V VCC and drives up to ten clock loads. One bank of ten outputs provide low-s.
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Meets or exceeds PC133 registered DIMM specification1.1 Spread Spectrum Clock Compatible Distributes one clock input to one bank of ten outputs Operating frequency 25MHz to 175MHz External feedback input (FBIN) terminal is used to synchrionize the outputs to the clock input No external RC network required Operates at 3.3V Vcc Plastic 24-pin 173mil TSSOP package
Block Diagram
FBOUT CLK0 CLK1 CLK2 FBIN CLKIN PLL CLK3 CLK4 AVCC CLK5 CLK6 CLK7 CLK8 CLK9 OE
Pin Configuration
AGND VCC CLK0 CLK1 CLK2 GND GND CLK3 CLK4 VCC OE FBOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 1.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | ICS2509C |
Integrated Circuit Systems |
3.3V Phase-Lock Loop Clock Driver | |
2 | ICS252 |
Integrated Circuit Systems |
Field Programmable Dual Output SS VersaClock Synthesizer | |
3 | ICS252BI09L |
Renesas |
VCXO Jitter Attenuator & Synchronous Multiplier | |
4 | ICS2572 |
Integrated Circuit Systems |
User-Programmable Dual High-Performance Clock Generator | |
5 | ICS2595 |
Integrated Circuit Systems |
User-Programmable Dual High-Performance Clock Generator | |
6 | ICS2002 |
Integrated Circuit Systems |
Wavedec Digital Audio Codec | |
7 | ICS2008B |
Integrated Circuit Systems |
SMPTE Time Code Receiver/Generator | |
8 | ICS2008B |
Renesas |
SMPTE Time Code Receiver/Generator | |
9 | ICS22002I-01 |
IDT |
CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER | |
10 | ICS2304NZ-1 |
Renesas |
LOW SKEW PCI/PCI-X BUFFER | |
11 | ICS2305 |
Integrated Circuit Systems |
3.3 VOLT ZERO DELAY / LOW SKEW BUFFER | |
12 | ICS2309 |
Integrated Circuit Systems |
3.3 VOLT ZERO DELAY / LOW SKEW BUFFER |