The ICS2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on ICS’ proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-sta.
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Clock outputs from 10 to 133 MHz Zero input-output delay Four low skew (<250 ps) outputs Device-to-device skew <700 ps Full CMOS outputs with 25 mA output drive capability at TTL levels 5 V tolerant CLKIN Tri-state mode for board-level testing Advanced, low power, sub-micron CMOS process Operating voltage of 3.3 V Industrial temperature range available Packaged in 8-pin SOIC Available in Pb (lead ) free package
Block Diagram
VDD
CLKIN
PLL
CLKOUT CLK1 CLK2 CLK3 CLK4
GND
MDS 2305 D I n t e gra te d C i r c u i t S y s te m s
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52 5 Ra ce Street, San Jose, CA 9 5.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | ICS2304NZ-1 |
Renesas |
LOW SKEW PCI/PCI-X BUFFER | |
2 | ICS2309 |
Integrated Circuit Systems |
3.3 VOLT ZERO DELAY / LOW SKEW BUFFER | |
3 | ICS2002 |
Integrated Circuit Systems |
Wavedec Digital Audio Codec | |
4 | ICS2008B |
Integrated Circuit Systems |
SMPTE Time Code Receiver/Generator | |
5 | ICS2008B |
Renesas |
SMPTE Time Code Receiver/Generator | |
6 | ICS22002I-01 |
IDT |
CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER | |
7 | ICS2402 |
IDT |
MULTIPLIER AND ZERO DELAY BUFFER | |
8 | ICS2494 |
Integrated Circuit Systems |
Dual Video / Memory Clock Generator | |
9 | ICS2494A |
Integrated Circuit Systems |
Dual Video / Memory Clock Generator | |
10 | ICS2495 |
Integrated Circuit Systems |
Dual Video/Memory Clock Generator | |
11 | ICS2509C |
Integrated Circuit Systems |
3.3V Phase-Lock Loop Clock Driver | |
12 | ICS2510C |
Integrated Circuit Systems |
3.3V Phase-Lock Loop Clock Driver |