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HYMP164S64CP6 - Hynix Semiconductor

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HYMP164S64CP6 1200pin Unbuffered DDR2 SDRAM SO-DIMMs

and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Dec. 2009 1 www.DataSheet4U.com 1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE & KEY PARAMETERS C4 (DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-tRCD-tRP 400 533 4-4-4 Y5 (DDR2.

Features


• JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply
• All inputs and outputs are compatible with SSTL_1.8 interface


• Posted CAS Programmable CAS Latency 3 ,4 ,5, and 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)




• Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60 ball(x8) , 84 ball(x16) FBGA

• 67.60 x 30.00 mm f.

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