HYMP112P72CP8-S5 - Hynix Semiconductor

HYMP112P72CP8-S5 240pin Registered DDR2 SDRAM DIMMs based on 1Gb

and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Jun. 2007 1 1240pin Registered DDR2 SDRAM DIMMs SPEED GRADE & KEY PARAMETERS E3 (DDR2-400) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 3-3-3 C4 (DDR2-533) 400 533 4-4-4 Y5 (DDR2-667) 400 .

Features

• JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination)
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• Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60 ball(x4/x8) 133.35 x 30.00 mm form factor RoHS .