HYMP112S64LMP8 - Hynix Semiconductor

HYMP112S64LMP8 DDR2 SDRAM SO-DIMM

and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ July 2004 1 www.DataSheet4U.com DDR2 SDRAM SO-DIMM HYMP112S64(L)MP8 DESCRIPTION 128Mx64 bits Hynix HYMP112S64MP8 series is unbuffered 200-pin double data rate 2 Synchronous DRAM Small Out.

Features

•
•
•
•
•
• 1GB (128M x 64) Unbuffered DDR2 SO - DIMM based on 128Mx8 DDR2 DDP SDRAMs JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differential clock operations (CK & /CK) Programmable CAS Latency 3 / 4 /5 supported
•
• Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 7.8us refresh period at Lower than TCASE 85℃, 3.9us( 85 ℃ ＜ TCASE ≤ 95℃)
• .