HYB39S128800FT - Qimonda

HYB39S128800FT 128-MBit Synchronous DRAM

The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabr.

Features

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• Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Packages: P(G)
  –TSOPII
  –54 400 mil width This chapter lists all main features of the product family HY[B/I]39S128[40/80/16][0/7]F[E/T](L) and the ordering information. Fully Synchronous to Positive Clock Edge 0 to 70 °C Standard Operating Temperature -40 to 85 °C Industrial Operating Temperature.