The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabr.
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• Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Packages: P(G)
–TSOPII
–54 400 mil width
This chapter lists all main features of the product family HY[B/I]39S128[40/80/16][0/7]F[E/T](L) and the ordering information.
Fully Synchronous to Positive Clock Edge 0 to 70 °C Standard Operating Temperature -40 to 85 °C Industrial Operating Temperature.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HYB39S128400FEL |
Qimonda |
128-MBit Synchronous DRAM | |
2 | HYB39S128400FT |
Qimonda |
128-MBit Synchronous DRAM | |
3 | HYB39S128400FTL |
Qimonda |
128-MBit Synchronous DRAM | |
4 | HYB39S128400CT |
Infineon Technologies |
128-MBit Synchronous DRAM | |
5 | HYB39S128400CTL |
Infineon Technologies |
128-MBit Synchronous DRAM | |
6 | HYB39S128407FE |
Qimonda |
128-MBit Synchronous DRAM | |
7 | HYB39S128160CT |
Infineon Technologies |
128-MBit Synchronous DRAM | |
8 | HYB39S128160CTL |
Infineon Technologies |
128-MBit Synchronous DRAM | |
9 | HYB39S128160FE |
Qimonda |
128-MBit Synchronous DRAM | |
10 | HYB39S128160FEL |
Qimonda |
128-MBit Synchronous DRAM | |
11 | HYB39S128160FT |
Qimonda |
128-MBit Synchronous DRAM | |
12 | HYB39S128160FTL |
Qimonda |
128-MBit Synchronous DRAM |