and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.5 / Aug. 2008 1 11 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2CLF(P) Series Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 1.1 1.2 Initial Draft Initial Draft.
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Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)
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MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write operation, a different bank is activated and burst Read or Write for that bank is performed - During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
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Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage inte.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HY5S5B2CLFP-HE |
Hynix Semiconductor |
256M (8Mx32bit) Mobile SDRAM | |
2 | HY5S5B2CLFP-SE |
Hynix Semiconductor |
256M (8Mx32bit) Mobile SDRAM | |
3 | HY5S5B2BLF-6E |
Hynix Semiconductor |
256M (8Mx32bit) Mobile SDRAM | |
4 | HY5S5B2BLF-HE |
Hynix Semiconductor |
256M (8Mx32bit) Mobile SDRAM | |
5 | HY5S5B2BLF-SE |
Hynix Semiconductor |
256M (8Mx32bit) Mobile SDRAM | |
6 | HY5S5B2BLFP-6E |
Hynix Semiconductor |
256M (8Mx32bit) Mobile SDRAM | |
7 | HY5S5B2BLFP-HE |
Hynix Semiconductor |
256M (8Mx32bit) Mobile SDRAM | |
8 | HY5S5B2BLFP-SE |
Hynix Semiconductor |
256M (8Mx32bit) Mobile SDRAM | |
9 | HY5S5B6ELF-HE |
Hynix Semiconductor |
256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O | |
10 | HY5S5B6ELF-SE |
Hynix Semiconductor |
256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O | |
11 | HY5S5B6ELFP-HE |
Hynix Semiconductor |
256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O | |
12 | HY5S5B6ELFP-SE |
Hynix Semiconductor |
256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O |