HY5S2B6DLFP-SE - Hynix Semiconductor

HY5S2B6DLFP-SE 4Banks x 2M x 16bits Synchronous DRAM

and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Feb. 2005 1 1HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix Mobile SDR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellu.

Features

Standard SDR Protocol Internal 4bank operation
● Voltage : VDD = 1.8V, VDDQ = 1.8V
● LVCMOS compatible I/O Interface
● Low Voltage interface to reduce I/O power
● Low Power Features - PASR(Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - Deep Power Down Mode
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● Programmable CAS latency of 1, 2 or 3 Pakage Type : 54Ball FBGA - HY5S2B6DLF : Lead - HY5S2B6DLFP : Lead Free ORDERING INFORMATION Part Number HY5S2B6DLF-SE 105MHz HY5S2B6DLFP-SE 4banks x 2Mb x 16 HY5S2B6DLF-BE 66MHz HY5S2B6DLFP-BE 2 Lead Free LVCMOS Lead 3 Lead Free Clock Frequ.