. . FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214B PROGRAMMABLE DOWNCONVERTER . . . . . . Functional Description . . . . .
• Up to 65 MSPS Front-End Processing Rates (CLKIN) and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous
• Processing Capable of >100dB SFDR
• Up to 255-Tap Programmable FIR
• Overall Decimation Factor Ranging from 4 to 16384
• Output Samples Rates to ≅ 12.94 MSPS with Output Bandwidths to ≅ 982kHz Lowpass
• 32-Bit Programmable NCO for Channel Selection and Carrier Tracking
• Digital Resampling Filter for Symbol Tracking Loops and Incommensurate Sample-to-Output Clock Ratios
• Digital AGC with Programmable Limits and Slew Rate to Optimize Output Signal Resolution; Fixed or A.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HSP50214A |
Intersil Corporation |
Programmable Downconverter | |
2 | HSP50210 |
Intersil Corporation |
Digital Costas Loop | |
3 | HSP50210 |
Renesas |
Digital Costas Loop | |
4 | HSP50215 |
Intersil Corporation |
Digital UpConverter | |
5 | HSP50216 |
Intersil Corporation |
Four-Channel Programmable Digital DownConverter | |
6 | HSP50016 |
Intersil Corporation |
Digital Down Converter | |
7 | HSP50110 |
Intersil Corporation |
Digital Quadrature Tuner | |
8 | HSP50306 |
Intersil Corporation |
Digital QPSK Demodulator | |
9 | HSP50307 |
Intersil Corporation |
Burst QPSK Modulator | |
10 | HSP50415 |
Intersil Corporation |
Wideband Programmable Modulator (WPM) | |
11 | HSP-1920 |
Digital View |
Component INTERFACE CONTROLLER | |
12 | HSP-4096 |
Digital View |
HDMI INTERFACE CONTROLLER |