HM658128A - Hitachi

HM658128A 131072-word x 8-bit High Speed CMOS Pseudo Static RAM

Symbol A0 to A16 I/O0 to I/O7 RFSH CE OE WE CS VCC VSS Pin name Address inputs Data input/output Refresh Chip enable Output enable Write enable Chip select Power supply Ground 3 HM658128A Series Block Diagram A0 Address latch control Row decoder Memory matrix (512 × 256) × 8 A8 I/O 0 www.DataSheet4U.com I/O 7 Input data control Column I/O Column dec.

Features

• Single 5 V (± 10%)
• High speed — Access time CE Access time: 80/100/120 ns — Cycle time Random read/ Write cycle time: 130/160/190 ns
• Low power: — Active: 300 mW (typ) — Standby: 350 µW (typ) (LL-version) 500 µW (typ) (L-version)
• All inputs and outputs TTL compatible
• Non multiplexed address
• 512 refresh cycles (8 ms)
• Refresh functions — Address refresh — Automatic refresh — Self refresh 8 mm × 20 mm 32-pin plastic TSOP reverse type (TFP-32DR) HM658128A Series Pin Arrangement HM658128ALP/ALFP Series RFSH A16 A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29.