HEF4724B - NXP

HEF4724B 8-bit addressable latch

The HEF4724B is an 8-bit addressable latch with three address inputs (A0 to A2), a data input (D), an active LOW enable input (E), an active HIGH clear input (CL), and eight parallel latch outputs (O0 to O7). When E and CL are HIGH, all outputs (O0 to O7) are LOW. Eight-channel demultiplexing or active HIGH 1-of-8 decoding with output enable operation occurs.

Features

GH, the contents of the latch are stored. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of A0 to A2 could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW). Fig.2 Pinning diagram. et4U.com DataSheet4U.com DataShee 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) HEF4724BP(N): HEF4724BD(F): HEF4724BT(D): ( ): Package Designator North America PINNING A0 to A2 Fig.1 Functional diagram. A E CL O0 to O7 address inputs data input enable .