HEF4011UB - NXP

HEF4011UB Quadruple 2-input NAND gate

The HEF4011UB is a quadruple 2-input NAND gate. This unbuffered single stage version provides a direct implementation of the NAND function. The output impedance and output transition time depends on the input voltage and input rise and fall times applied. HEF4011UB gates Fig.2 Pinning diagram. HEF4011UBP(N): Fig.1 Functional diagram. HEF4011UBD(F): HEF401.

Features

s provide identical inputs. FAMILY DATA, IDD LIMITS category GATES See Family Specifications for VIH/VIL unbuffered stages January 1995 2 Philips Semiconductors Product specification Quadruple 2-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW LOW to HIGH Input capacitance 10 15 5 10 15 5 10 15 CIN tTLH tTHL tPLH tPHL 60 25 20 35 20 17 75 30 20 60 30 20 120 50 40 70 40 35 150 60 40 110 60 40 10 ns ns ns ns ns ns ns ns ns ns ns ns pF S.