HEF4001UB - NXP

HEF4001UB Quadruple 2-input NOR gate

The HEF4001UB is a quadruple 2-input NOR gate. This unbuffered single stage version provides a direct implementation of the NOR function. The output impedance and output transition time depends on the input voltage and input rise and fall times applied. HEF4001UB gates Fig.2 Pinning diagram. HEF4001UBP(N): 14-lead DIL; plastic (SOT27-1) HEF4001UBD(F): 14-.

Features

ffered stages Fig.3 Schematic diagram (one gate). The splitting-up of the p-transistors provide identical inputs. January 1995 2 Philips Semiconductors Product specification Quadruple 2-input NOR gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Input capacitance 10 15 CIN tTLH tTHL tPLH tPHL 65 30 25 40 20 15 75 30 20 60 30 20 − 130 60 50 80 40 30 150 60 40 110 60 40 10 ns ns ns ns ns ns ns ns ns ns ns ns pF 30 ns 17.