The HD74 LVC374A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input. When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again. W.
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• VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25 °C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@VCC = 3.0 V to 5.5 V)
HD74LVC374A
Function Table
Inputs G H L L L H: L: X: Z: ↑: Q0 : CK X ↑ ↑ L D X L H X Output Q Z L H Q0
High level Low level Immaterial High impedance Low to high transition Level of Q before the indicated steady input conditions were established.
Pin Arrangement
G 1 1Q 2 1D 3 .
The HD74 LVC374A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D in.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HD74LVC373A |
Hitachi Semiconductor |
Octal D-type Transparent | |
2 | HD74LVC373A |
Renesas |
Octal D-type Transparent Latches | |
3 | HD74LVC32 |
Hitachi Semiconductor |
Quad. 2-input OR Gates | |
4 | HD74LVC32 |
Renesas |
Quad. 2-input OR Gates | |
5 | HD74LVC00 |
Hitachi Semiconductor |
Quad. 2-input NAND Gates | |
6 | HD74LVC00 |
Renesas |
Quad. 2-input NAND Gates | |
7 | HD74LVC02 |
Hitachi Semiconductor |
Quad. 2-input NOR Gates | |
8 | HD74LVC02 |
Renesas |
Quad. 2-input NOR Gates | |
9 | HD74LVC04 |
Hitachi Semiconductor |
Hex Inverters | |
10 | HD74LVC04 |
Renesas |
Hex Inverters | |
11 | HD74LVC08 |
Hitachi Semiconductor |
Quad. 2-input AND Gates | |
12 | HD74LVC08 |
Renesas |
Quad. 2-input AND Gates |