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The HD74LVC373A has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outp.
• VCC = 2.0 V to 5.5 V
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state)
• Typ.
HD74LVC373A - Hitachi Semiconductor
The HD74LVC373A has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is hi.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | HD74LVC374A |
Hitachi Semiconductor |
Octal D-type Flip Flops with 3-state Outputs |
|
| 2 | HD74LVC374A |
Renesas |
Octal D-type Flip Flops |
|
| 3 | HD74LVC32 |
Hitachi Semiconductor |
Quad. 2-input OR Gates |
|
| 4 | HD74LVC32 |
Renesas |
Quad. 2-input OR Gates |
|
| 5 | HD74LVC00 |
Hitachi Semiconductor |
Quad. 2-input NAND Gates |
|
| 6 | HD74LVC00 |
Renesas |
Quad. 2-input NAND Gates |
|
| 7 | HD74LVC02 |
Hitachi Semiconductor |
Quad. 2-input NOR Gates |
|
| 8 | HD74LVC02 |
Renesas |
Quad. 2-input NOR Gates |
|
| 9 | HD74LVC04 |
Hitachi Semiconductor |
Hex Inverters |
|
| 10 | HD74LVC04 |
Renesas |
Hex Inverters |
|
| 11 | HD74LVC08 |
Hitachi Semiconductor |
Quad. 2-input AND Gates |
|
| 12 | HD74LVC08 |
Renesas |
Quad. 2-input AND Gates |
|