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The HD74LV374A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input. When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again. Whe.
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO.
HD74LV374A - Hitachi Semiconductor
The HD74LV374A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D inpu.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | HD74LV373A |
Hitachi Semiconductor |
Octal D-type Transparent Latches with 3-state Outputs |
|
| 2 | HD74LV373A |
Renesas |
Octal D-type Transparent Latches |
|
| 3 | HD74LV32A |
Hitachi Semiconductor |
Quad. 2-input OR Gates |
|
| 4 | HD74LV32A |
Renesas |
Quad. 2-input OR Gates |
|
| 5 | HD74LV393A |
Hitachi Semiconductor |
Dual 4-bit Binary Counters |
|
| 6 | HD74LV393A |
Renesas |
Dual 4-bit Binary Counters |
|
| 7 | HD74LV00A |
Hitachi Semiconductor |
Quad. 2-input NAND Gates |
|
| 8 | HD74LV00A |
Renesas |
2-input NAND Gates |
|
| 9 | HD74LV02A |
Hitachi Semiconductor |
Quad. 2-input NOR Gates |
|
| 10 | HD74LV02A |
Renesas |
2-input NOR Gates |
|
| 11 | HD74LV04A |
Hitachi Semiconductor |
Hex Inverters |
|
| 12 | HD74LV04A |
Renesas |
Hex Inverters |
|