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The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established. And when both inputs are low, output is high, but this high level are uncon.
• High Speed Operation: tpd (S to Q) = 10 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code (Previous Code)
Package Abbreviation
HD74HC279FPEL SOP-16 pin (JEITA)
PRSP0016DH-B (FP-16DAV)
FP
HD74HC279RPEL SOP-16 pin (JEDEC)
.
HD74HC279 - Hitachi Semiconductor
The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When ei.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | HD74HC27 |
Hitachi Semiconductor |
Triple 3-input NOR Gates |
|
| 2 | HD74HC27 |
Renesas |
Triple 3-input NOR Gates |
|
| 3 | HD74HC273 |
Hitachi Semiconductor |
Octal D-type Flip-Flops (with Clear) |
|
| 4 | HD74HC273 |
Renesas |
Octal D-type Flip-Flops |
|
| 5 | HD74HC20 |
Hitachi Semiconductor |
Dual 4-input NAND Gates |
|
| 6 | HD74HC20 |
Renesas |
Dual 4-input NAND Gates |
|
| 7 | HD74HC21 |
Hitachi Semiconductor |
Dual 4-input AND Gates |
|
| 8 | HD74HC21 |
Renesas |
Dual 4-input AND Gates |
|
| 9 | HD74HC221 |
Hitachi Semiconductor |
Dual Monostable Multivibrators (with Schmitt Trigger Input) |
|
| 10 | HD74HC221 |
Renesas |
Dual Monostable Multivibrators |
|
| 11 | HD74HC237 |
Hitachi Semiconductor |
3-to-8-line Decoder/Demultiplexer with Address Latch |
|
| 12 | HD74HC237 |
Renesas |
3-to-8-line Decoder/Demultiplexer |
|