The Intersil HCS161MS is a Radiation Hardened 4-Input Binary; synchronous counter featuring asynchronous reset and look-ahead carry logic. The HCS161 has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs (p0 - p3) to load the counter. The data is latched to the .
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity 2 x 10-9 Error/Bit Day
(Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.3 VCC Max - VIH = 0.7 VCC Min
• Input Current Levels Ii .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HCS160MS |
Intersil |
Radiation Hardened BCD Decade Synchronous Counter | |
2 | HCS163MS |
Intersil |
Radiation Hardened Synchronous Presettable Counter | |
3 | HCS164MS |
Intersil |
Radiation Hardened 8-Bit Serial-In/Parallel-Out Register | |
4 | HCS165MS |
Intersil |
Radiation Hardened Inverting 8-Bit Parallel-Input/Serial Output Shift Register | |
5 | HCS166MS |
Intersil |
Radiation Hardened 8-Bit Parallel-Input/Serial Output Shift Register | |
6 | HCS101 |
Microchip |
Fixed Code Encoder | |
7 | HCS109MS |
Intersil |
Radiation Hardened Dual JK Flip Flop | |
8 | HCS10MS |
Intersil |
Radiation Hardened Triple 3-Input NAND Gate | |
9 | HCS112MS |
Intersil Corporation |
Radiation Hardened Dual JK Flip-Flop | |
10 | HCS11MS |
Intersil |
Radiation Hardened Triple 3-Input AND Gate | |
11 | HCS12 |
Motorola Inc |
USB2.0 to ATA/ATAPI Bridge | |
12 | HCS1206 |
HITANO |
METAL STRIP CURRENT SENSING RESISTORS |