FDG6321C - ON Semiconductor

FDG6321C Dual-Channel Digital FET

These dual N & P−Channel logic level enhancement mode field effect transistors are produced using onsemi’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on−state resistance. This device has been designed especially on low voltage replacement for bipolar digital transistors and small signal .

Features

• N−Ch 0.50 A, 25 V ♦ RDS(ON) = 0.45 W @ VGS = 4.5 V ♦ RDS(ON) = 0.60 W @ VGS = 2.7 V
• P−Ch −0.41 A, −25 V ♦ RDS(ON) = 1.1 W @ VGS = −4.5 V ♦ RDS(ON) = 1.5 W @ VGS = −2.7 V
• Very Small Package Outline SC70−6
• Very Low Level Gate Drive Requirements Allowing Direct Operation in 3 V Circuits (VGS(th) < 1.5 V)
• Gate−Source Zener for ESD Ruggedness (>6 kV Human Body Model)
• These Devices are Pb−Free and are RoHS Compliant ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Symbol Parameter N−Channel P−Channel Units VDSS Drain−Source Voltage 25 VGSS Gate−Source Voltage 8 ID Dr.