EPM3256A - Altera

EPM3256A Programmable Logic

■ PCI compatible ■ Bus–friendly architecture including programmable slew–rate control ■ Open–drain output option ■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls ■ Programmable power–saving mode for a power reduction of over 50% in each macrocell ■ Configurable expander product–term distribution, allowing up.

Features

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■ High
  –performance, low
  –cost CMOS EEPROM
  –based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built
  –in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
  – ISP circuitry compliant with IEEE Std. 1532
■ Built
  –in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Enhanced ISP features:
  – Enhanced ISP algorithm for faster programming
  – ISP_Done bit to ensure complete programming
  – Pull-up resistor on I/O pins during in
  –system programming
■ High
  –d.