■ PCI compatible ■ Bus–friendly architecture including programmable slew–rate control ■ Open–drain output option ■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls ■ Programmable power–saving mode for a power reduction of over 50% in each macrocell ■ Configurable expander product–term distribution, allowing up.
..
■ High
–performance, low
–cost CMOS EEPROM
–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built
–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
■ Built
–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in
–system programming
■ High
–d.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | EPM3032A |
Altera |
Programmable Logic | |
2 | EPM3064A |
Altera |
Programmable Logic | |
3 | EPM3256A |
Altera |
Programmable Logic | |
4 | EPM3512A |
Altera |
Programmable Logic | |
5 | EPM-14 |
VERSALOGIC |
AMD LX 800 Based SBC | |
6 | EPM-4 |
VERSALOGIC |
AMD processor module | |
7 | EPM-4001 |
TE |
SpO2 Optical Sensor | |
8 | EPM-5 |
VERSALOGIC |
AMD GX Based SBC | |
9 | EPM1270 |
Altera Corporation |
(EPMxxxx) JTAG & In-System Programmability | |
10 | EPM2210 |
Altera Corporation |
(EPMxxxx) JTAG & In-System Programmability | |
11 | EPM240 |
Altera Corporation |
(EPMxxxx) JTAG & In-System Programmability | |
12 | EPM5016 |
Altera |
(EPM5016 - EPM5192) High Speed High Density MAX 5000 Devices |