EM669325 - Etron Technology

EM669325 4M x 32 Low Power SDRAM

Symbol Type Description CLK 4M x 32 LPSDRAM EM669325 Table 1. Pin Details of 4Mx32 LPSDRAM Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK .

Features

Clock rate: 133/125/100 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (1M x 32bit x 4bank) Programmable Mode - CAS# Latency: 1, 2 & 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential & Interleave - Burst-Read-Single-Write
• Burst stop function
• Individual byte controlled by DQM0-3
• Auto Refresh and Self Refresh
•
•
•
•
• EM669325 Preliminary (Rev 0.6 Sep./2003)
• 4096 refresh cycles/64ms
• Single 3.0V, or 3.3V power supply
• Interface: LVTTL
•Package : 90 ball-FBGA, 11x13mm, Lead Free 4M x 32 Low Power SDRAM (LPSDRAM) Ordering Informa.