D3NB50 - STMicroelectronics

D3NB50 STD3NB50

Using the latest high voltage MESH OVERLAY™ process, SGS-Thomson has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and s.

Features

tot dv/dt( 1 ) T stg Tj May 1998 Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω ) Gate-source Voltage Drain Current (continuous) at T c = 25 C Drain Current (continuous) at T c = 100 C Drain Current (pulsed) Total Dissipation at T c = 25 o C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature o o Value 500 500 ± 30 3 1.9 12 50 0.4 4.5 -65 to 150 150 (1) ISD ≤3A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX Unit V V V A A A W W/ o C V/ns o o C C 1/6 (
•) Pulse width limited by safe operating area This is pre.