CY7C4121KV13/CY7C4141KV13 144-Mbit QDR™-IV HP SRAM 144-Mbit QDR™-IV HP SRAM Features ■ 144-Mbit density (8M ×18, 4M ×36) ■ Total Random Transaction Rate [1] of 1334 MT/s ■ Maximum operating frequency of 667 MHz ■ Read latency of 5.0 clock cycles and write latency of 3.0 clock cycles ■ Two-word burst on all accesses ■ Dual independent bidirectional data port.
■ 144-Mbit density (8M ×18, 4M ×36)
■ Total Random Transaction Rate [1] of 1334 MT/s
■ Maximum operating frequency of 667 MHz
■ Read latency of 5.0 clock cycles and write latency of 3.0 clock cycles
■ Two-word burst on all accesses
■ Dual independent bidirectional data ports
❐ Double data rate (DDR) data ports
❐ Supports concurrent read/write transactions on both ports
■ Single address port used to control both data ports
❐ DDR address signaling
■ Single data rate (SDR) control signaling
■ High-speed transceiver logic (HSTL) and stub series terminated logic (SSTL) compatible signaling (JESD8-1.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | CY7C4142KV13 |
Cypress Semiconductor |
144-Mbit QDR-IV XP SRAM | |
2 | CY7C4121KV13 |
Cypress Semiconductor |
144-Mbit QDR-IV HP SRAM | |
3 | CY7C4122KV13 |
Cypress Semiconductor |
144-Mbit QDR-IV XP SRAM | |
4 | CY7C419 |
Cypress |
256/512/1K/2K/4K x 9 Asynchronous FIFO | |
5 | CY7C401 |
Cypress Semiconductor |
(CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO | |
6 | CY7C402 |
Cypress Semiconductor |
(CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO | |
7 | CY7C4021KV13 |
Cypress Semiconductor |
72-Mbit QDR-IV HP SRAM | |
8 | CY7C403 |
Cypress Semiconductor |
(CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO | |
9 | CY7C404 |
Cypress Semiconductor |
(CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO | |
10 | CY7C4041KV13 |
Cypress Semiconductor |
72-Mbit QDR-IV HP SRAM | |
11 | CY7C408A |
Cypress |
64 x 8 Cascadable FIFO | |
12 | CY7C409A |
Cypress |
64 x 9 Cascadable FIFO |