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The CY7C401 and CY7C403 are asynchronous first-in first-out (FIFOs) organized as 64 four-bit words. The CY7C402 and CY7C404 are similar FIFOs organized as 64 five-bit Logic Block Diagram SI IR INPUT CONTROL LOGIC Pin Configurations DIP WRITE POINTER (CY7C401) NC (CY7C403) OE IR SI DI 0 DI 1 DI 2 DI 3 GND 1 16 2 15 3 14 CY7C401 4 13 CY7C403 5 12 6 11 10 7 9.
• 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO)
• Processed with high-speed CMOS for optimum speed/power
• 25-MHz data rates
• 50-ns bubble-through time—25 MHz
• Expandable in word width and/or length
• 5-volt power supply ± 10% tolerance, both commercial and military
• Independent asynchronous inputs and outputs
• TTL-compatible interface
• Output enable function available on CY7C403 and CY7C404
• Capable of withstanding greater than 2001V electrostatic discharge
• Pin compatible with MMI 67401A/67402A words. Both the CY7C403 and CY7C404.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | CY7C401 |
Cypress Semiconductor |
(CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO |
|
| 2 | CY7C4021KV13 |
Cypress Semiconductor |
72-Mbit QDR-IV HP SRAM |
|
| 3 | CY7C403 |
Cypress Semiconductor |
(CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO |
|
| 4 | CY7C404 |
Cypress Semiconductor |
(CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO |
|
| 5 | CY7C4041KV13 |
Cypress Semiconductor |
72-Mbit QDR-IV HP SRAM |
|
| 6 | CY7C408A |
Cypress |
64 x 8 Cascadable FIFO |
|
| 7 | CY7C409A |
Cypress |
64 x 9 Cascadable FIFO |
|
| 8 | CY7C4121KV13 |
Cypress Semiconductor |
144-Mbit QDR-IV HP SRAM |
|
| 9 | CY7C4122KV13 |
Cypress Semiconductor |
144-Mbit QDR-IV XP SRAM |
|
| 10 | CY7C4141KV13 |
Cypress Semiconductor |
144-Mbit QDR-IV HP SRAM |
|
| 11 | CY7C4142KV13 |
Cypress Semiconductor |
144-Mbit QDR-IV XP SRAM |
|
| 12 | CY7C419 |
Cypress |
256/512/1K/2K/4K x 9 Asynchronous FIFO |
|