CY7C1513AV18 - Cypress Semiconductor

CY7C1513AV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture

The CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and CY7C1515AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inpu.

Features

■ Configurations CY7C1511AV18
  – 8M x 8 CY7C1526AV18
  – 8M x 9 CY7C1513AV18
  – 4M x 18 CY7C1515AV18
  – 2M x 36 Separate independent read and write data ports
❐ Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in hi.