CY7C1427AV18 - Cypress Semiconductor

CY7C1427AV18 (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture

The CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered .

Features

• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
• 250-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL out.