CY2XP306 - Cypress Semiconductor

CY2XP306 High-frequency Programmable PECL Clock Generation Module

CY2XP306 PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table No Connect SER_DATA Serial Interface Data SER_CLK Serial Interface Clock Example PLL Output Frequency 311.04.

Features

• 60 ps typical Cycle-to-Cycle Jitter
• 30 ps typical Output-Output Skew
• Phase-locked loop (PLL) multiplier select
• LVTTL or XO Input; Six LVPECL Outputs
• Selectable Output Divider (/2)
• 1
  –133 MHz Input Frequency Range
• 62.5
  –500 MHz Output Frequency Range
• 36-pin VFBGA, 6 × 8 × 1 mm
• 3.3V operation
• Serially Configurable Multiply Ratios Block Diagram QA1 FSELA QA1# PLL_MULT 0 1 QA2 QA2# QA3 QA3# QB1 XIN/REF XOUT SER CLK SER DATA MR XTAL OSCILLATOR PLL xM /1 /2 0 1 QB1# QB2 QB2# QB3 FSELB QB3# Pin Configuration (Top View) C Y 2 X P 3 0 6 3 6 V F B G A P IN C O N F IG U R A .