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3.3V Power Supply for Crystal Driver SER_CLK Serial Interface Clock SER_DATA Serial Interface Data PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table CLK_SEL INA,INAB NC Clock Select Input, Internal Pull down. HIGH select INA/INAB, Internal PLL is bypassed. LOW select internal PLL Differential Clock Input pair, used in PLL-.
• Period jitter peak-peak 125MHz(max.) = 55 ps
• Four low-skew LVPECL outputs
• Phase-locked loop (PLL) multiplier select
• Serially-configurable multiply ratios
• Eight-bit feedback counter and six-bit reference counter for high accuracy
• HSTL inputs—HSTL-to-LVPECL level translation
• 125- to 500-MHz output range for high-speed applications
• High-speed PLL bypass mode to 1.5 GHz
• 36-VFBGA, 6 × 8 × 1 mm
• 3.3V operation
Block Diagram
PLL_MULT CLK0 CLK0B CLK1 XIN XOUT SER CLK SER DATA INA INAB CLK_SEL XTAL OSCILLATOR PLL xM
0 1
CLK1B CLK2 CLK2B CLK3 CLK3B
Pin Configuration
C Y 2 X P 3 0 .
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | CY2XP306 |
Cypress Semiconductor |
High-frequency Programmable PECL Clock Generation Module |
|
| 2 | CY2XP31 |
Cypress Semiconductor |
312.5 MHz LVPECL Clock Generator |
|
| 3 | CY2XP311 |
Cypress Semiconductor |
312.5 MHz LVPECL Clock Generator |
|
| 4 | CY2XP21 |
Cypress Semiconductor |
125 MHz LVPECL Clock Generator |
|
| 5 | CY2XP22 |
Cypress Semiconductor |
Crystal to LVPECL Clock Generator |
|
| 6 | CY2XP24 |
Cypress Semiconductor |
Crystal to LVPECL Clock Generator |
|
| 7 | CY2XP41 |
Cypress Semiconductor |
Crystal to LVPECL Clock Generator |
|
| 8 | CY2X013 |
Cypress Semiconductor |
High-Performance LVDS Oscillator |
|
| 9 | CY2X0137 |
Cypress Semiconductor |
High-Performance LVDS Oscillator |
|
| 10 | CY2X014 |
Cypress Semiconductor |
Low-Jitter LVPECL Crystal Oscillator |
|
| 11 | CY2X0147 |
Cypress Semiconductor |
Low-Jitter LVPECL Crystal Oscillator |
|
| 12 | CY2XF23 |
Cypress Semiconductor |
High Performance LVDS Oscillator |
|